chip verification is becoming an increasingly complex task, driven by the rapid growth of large language models and the need for high-performance, low-latency systems at the edge. To address these challenges, Synopsys has introduced advancements in its hardware-assisted verification (HAV) portfolio, which now includes new platforms and capabilities that aim to scale verification productivity while meeting aggressive time-to-market demands.
The company’s software-defined HAV solutions, built around the ZeBu and HAPS platforms, are designed to support the verification of sophisticated multi-die and AI chips. These platforms leverage modular hardware and continuous software updates to deliver compounding performance gains, increased debug productivity, and expanded use case capabilities. The latest updates allow for broader application coverage, enabling teams to run quadrillions of verification cycles before silicon is ready.
One key focus is the industry’s highest capacity-scalable emulation platform, ZeBu Server 5, which now supports complex designs for data center AI training and inference, GPU workloads, custom accelerators, and networking IPU/DPU applications. The new HAPS-200 12 FPGA system, built with AMD’s Versal Premium VP1902 adaptive SoCs, offers 2x higher capacity compared to previous generations, while the HAPS-200 1 FPGA serves as a desktop solution for IP verification and software bring-up.
These advancements are particularly relevant for companies developing AI-driven systems, where verification must scale just as quickly as the models themselves. For instance, large language models double in size roughly every four months, while interface data rates advance at a 2x rate every three years. This rapid evolution demands HAV solutions that can handle both the complexity of multi-die architectures and the performance requirements of edge AI applications.
Synopsys’ software-defined approach also extends the lifetime value of its hardware platforms through continuous software improvements. This includes new Hardware-Assisted Test Solutions for processor, memory, and I/O subsystem validation, as well as fault emulation capabilities that enable scalable testing across RTL simulation, emulation, and prototyping. Additionally, Real-Number Models (RNM) emulation supports mixed-signal designs by providing fast, scalable abstraction of analog behavior within digital-centric verification flows.
For enterprises building large-scale AI infrastructure, such as AMD’s Helios solution, these platforms provide the scalability and versatility needed to verify complex subsystems—including CPUs, GPUs, and AI accelerators—while also accommodating growing software stacks. The ability to reconfigure hardware across projects and seamlessly transition between emulation and prototyping is critical for delivering high-performance, interoperable AI systems at scale.
The new HAPS-200 12 FPGA platform is available today, with the ZeBu-200 12 FPGA expected in Q3 2026. These updates reflect Synopsys’ commitment to meeting the evolving demands of AI chip verification, ensuring that hardware and software development can keep pace with the rapid advancements in AI technology.
